1. Technical Field
The embodiments herein generally relate to electronics circuits, and, more particularly, to a digital phase-locked loop (PLL) electronic circuit.
2. Description of the Related Art
Phase-locked loops (PLLs) are an integral part of many electronic circuits and are particularly important in communication circuits. For example, digital systems use clock signals to trigger synchronous circuits (e.g., flip-flops). Transmitter and receiver systems use local oscillator (LO) signals for frequency up-conversion and down-conversion, respectively. A wireless device (e.g., cellular phones) in wireless communication systems typically uses clock signals for digital circuitry and LO signals for transmitter and receiver circuitry. Clock and LO signals are often generated with phase-locked loops.
FIG. 1(A) shows a conventional integer PLL 100, which generally consists of a crystal oscillator 114, a phase frequency detector (PFD) 111, a loop filter (LF) 120, a voltage controlled oscillator (VCO) 112, and a divider 113. VCO 112 generates an oscillator signal having a frequency determined by a control signal from LF 120. Divider 113 divides the oscillator signal input frequency by a factor of N, whereby N is an integer, and provides a feedback signal. PFD 111 receives a reference signal and the feedback signal, compares the phases of the two signals, and provides a detector signal that is proportional to the detected phase difference or error between the two signals. LF 120 filters the detector signal and provides the control signal for VCO 112. Moreover, LF 120 adjusts the control signal such that the phase of the feedback signal is locked to that of the reference signal.
Generally, one of the main limitations of a conventional PLL 100 is that the output frequency is limited to be an integer multiple of the input frequency. This can be quite problematic for system-on-chip (SOC) and software defined radios (SDRs) where multiple standards and multiple applications are integrated on one chip. If an integer PLL 100 is used, then multiple external crystal oscillators 114 must typically be used, which tends to increase the board area, cost, and generally limits the ability to integrate higher level functions on one board. For this reason, a fractional-N PLL 150 is often used, as shown in FIG. 1(B).
The fractional-N PLL 150 periodically switches between two adjacent division ratios, N and N+1, in such a way that the average division ratio, N.F, is the desired division ratio. This is accomplished by a dual modulus frequency divider 152. The instantaneous frequency division value of the dual modulus divider 152 is controlled by the carry out signal of an accumulator 151. The input to the accumulator 151 is the digital representation of the desired fractional division ratio, F. The averaging is performed by the closed loop PLL low-pass filter response. Using this method, frequency steps less than the input crystal oscillator frequency can be obtained. Since fractional-N PLLs generally achieve an average division ratio N.F by periodically switching between N and N+1, the PLL output spectrum tends to contain undesired tonal signals at exactly the desired fractional values and their harmonics. Typically, these tonal signals can only be attenuated by the closed loop low-pass filter response of the PLL 150. For very small fractional values, the cut-off frequency of the low-pass filter may be very narrow, necessitating an off-chip loop filter.
Another alternative is to select the choice of N and N+1 by a digital sigma-delta modulator 202 as shown in FIG. 2. The PLL 200 in FIG. 2 is known as a sigma-delta PLL 200. The advantage of a sigma-delta PLL 200 is that it converts low-frequency tones into high-frequency quantization noise, as shown in FIG. 3. This enables a substantial reduction in the size of the LF 120, enabling the LF 120 to be integrated on-chip. The function of the LF 120 then becomes to filter out the high-pass filtered quantization noise instead of low-frequency in-band tones.
The sigma-delta PLL 200 is similar to a conventional fractional-N PLL 150, but differs in some respects. The dual modulus divider 152 and accumulator 151 are substituted with a multimodulus divider 201 and a digital sigma delta modulator 202, as shown in FIG. 2. The main disadvantage of a conventional fractional-N PLL 150 is that the choice of N and N+1 division ratios is chosen in a periodic fashion. This periodic behavior results in tonal output response which heavily degrades the output spectrum of the PLL 150. A sigma-delta PLL 200 uses a digital sigma-delta modulator 202 to randomize the choice between N and N+1. Indeed, a sigma-delta modulator 202 can be of higher order than 1, meaning the output of the sigma-delta modulator 202 can be greater than 1 bit. This means that a dual-modulus divider is insufficient and a multimodulus divider 201 is necessary to dither (modulate) the choice of frequency division value from N−b1 to N+b2, where −b1 is the minimum level produced by the digital sigma-delta modulator 202 and +b2 is the maximum level produced by the digital sigma-delta modulator 202.
Although effective compared to a fractional-N PLL 150, a sigma-delta PLL 200 still generally suffers from several shortcomings. First, the sigma-delta quantization noise is typically still too high. To sufficiently attenuate high-frequency quantization noise, the loop filter corner frequency must generally be brought sufficiently low. This may result in a PLL implementation where the area is dominated by large LF capacitors. Reducing the closed loop bandwidth also typically means that less VCO phase noise is suppressed. This is less problematic if a high-Q resonance inductance-capacitance (LC) tank is used to implement the VCO 112. However, in most clock generator applications, a compact ring oscillator-based VCO is used, which has a notoriously high-phase noise. In these types of applications, the minimum total integrated phase noise, or jitter, produced by the PLL 200 is generally limited by equally balancing the jitter due to the sigma-delta quantization noise and the jitter due to the VCO phase noise.
Second, the analog implementation of the PLL 200 typically necessitates high linearity in the PFD 111. Since any mismatch or non-linearity in the PFD 111 can result in unequal step sizes or non-uniform sampling of the output of the divider 113, this can result in degradation in the high-pass noise shaping function of the sigma-delta modulator 202, which may lead to excessive in-band phase noise, and hence degradation of the performance of the PLL 200.
Third, analog PLL design is generally prone to various disadvantages. In an analog PLL, the LF 120 is generally implemented with analog circuit components (e.g., capacitors and resistors). One disadvantage of an analog implementation of a PLL 100, 150, 200 is large die area for the LF capacitors (which can occupy as much as 50% of the total area of the PLL 100, 150, 200). A second disadvantage is significant noise coupling through the substrate for a SOC design can seriously degrade the performance of the PLL 100, 150, 200. A third disadvantage is large undesired reference tones in the oscillator signal can develop due to gate leakage in the LF capacitors. Gate leakage generally increases exponentially with the reduction in oxide thickness and is thus more problematic as integrated circuit (IC) technology scales smaller.
A digital PLL avoids the disadvantages described above for the analog PLL. However, a major challenge for a digital fractional-N PLL design is obtaining a wide closed loop bandwidth while minimizing the spurious fractional-N tones or sigma-delta quantization noise. Wide loop bandwidth is generally desired for better tracking of the reference signal, which then reduces the amount of phase noise generated by the VCO and results in lower jitter. Jitter is the deviation from the average or expected cycle of the reference signal. In one conventional method, sigma-delta quantization noise is attenuated by subtracting an error term from the loop filter. However, this method is generally performed in the analog domain and may severely limit the achievable performance and generally impractically increases the die area. Therefore, there is a need in the art for a fractional-N digital PLL with improved performance and reduced jitter characteristics.